Recently, system LSIs including digital circuits and analog circuits mixedly built on one chip are being extensively fabricated using CMOS technology which is cheaper.
In such an LSI, an A/D converter for converting an analog signal into a set of digital signals and a D/A converter for converting a set of digital signals into an analog signal are used in an interface with the outside of the LSI.
When such an LSI is used for imaging or communications, a current steering D/A converter capable of a high speed operation is indispensable.
FIG. 13 shows the circuit configuration of a conventional current steering D/A converter 100. In this drawing, conversion of 8-bit digital signals into an analog signal is exemplified.
A voltage generated by a bias circuit 104 is applied to a first bias voltage terminal VB1 and a second bias voltage terminal VB2 of each of current sources IS1, IS2 and IS3-1 through IS3-63. A Current output from each of the current sources IS1, IS2 and IS3-1 through IS3-63 is allowed to flow to an analog output terminal OUT or a ground power supply VSS respectively by a corresponding one of differential switches SW1, SW2 and SW3-1 through SW3-63 controlled in accordance with a set of digital input signals. An analog current output in accordance with the digital input signals can be obtained from the analog output terminal OUT. The analog output current is converted into a voltage by an output load resistor 101.
The current source IS1 is a 1LSB (least significant bit) current source and the current source IS2 is a 2LSB current source. Also, the current sources IS3-1 through IS3-63 are 4LSB current sources and are sixty-three in total in number. By combining currents supplied from these current sources, analog outputs of 256 (=28) tones can be obtained.
The bias circuit 104 generates two bias voltages VB1 and VB2 in accordance with a voltage supplied from a reference voltage generator circuit 103 to its reference voltage input terminal VREF and an external resistor 102 connected to its reference resistor connecting terminal IREF.
Furthermore, a decoder circuit 105 decodes 8-bit digital signals input to its digital input terminals IN0 through IN7 for outputting differential switch control signals D1, D2 and D3-1 through D3-63.
Each current source used in this conventional current steering D/A converter has the following circuit configuration:
FIG. 14 shows a first exemplified circuit configuration of the conventional current sources. In FIG. 14, in a current source 111, the source terminal of a P-channel transistor Tr111 with a channel length L1 and a channel width W1 is connected to a power supply VDD, the gate terminal thereof is connected to a first bias voltage terminal VB1 and the drain terminal thereof is connected to the source terminal of a P-channel transistor Tr112 with a channel length L2 and a channel width W1, and the gate terminal of the transistor Tr112 is connected to a second bias voltage terminal VB2 and the drain terminal thereof is connected to a current output terminal Iout111. Thus, the current source 111 is able to output a current with a current value corresponding to 1LSB.
Furthermore, in a current source 112, the source terminal of a P-channel transistor Tr113 with a channel length L1 and a channel width W1 is connected to a power supply VDD, the gate terminal thereof is connected to a first bias voltage terminal VB1 and the drain terminal thereof is connected to the source terminal of a P-channel transistor Tr114 with a channel length L2 and a channel width W1, and the gate terminal of the transistor Tr114 is connected to a second bias voltage terminal VB2 and the drain terminal thereof is connected to a current output terminal Iout112, and the source terminal of a P-channel transistor Tr115 with a channel length L1 and a channel width W1 is connected to a power supply VDD, the gate terminal thereof is connected to the first bias voltage terminal VB1 and the drain terminal thereof is connected to the source terminal of a P-channel transistor Tr116 with a channel length L2 and a channel width W1, and the gate terminal of the transistor Tr116 is connected to the second bias voltage terminal VB2 and the drain terminal thereof is connected to the current output terminal Iout112. Thus, the current source 112 is able to output a current with a current value corresponding to 2LSB.
Moreover, in a current source 113, the source terminal of a P-channel transistor Tr117 with a channel length L1 and a channel width W1 is connected to a power supply VDD, the gate terminal thereof is connected to a first bias voltage terminal VB1 and the drain terminal thereof is connected to the source terminal of a P-channel transistor Tr118 with a channel length L2 and a channel width W1. The gate terminal of the transistor Tr118 is connected to a second bias voltage terminal VB2 and the drain terminal thereof is connected to a current output terminal Iout113, and the source terminal of a P-channel transistor Tr119 with a channel length L1 and a channel width W1 is connected to a power supply VDD, the gate terminal thereof is connected to the first bias voltage terminal VB1 and the drain terminal thereof is connected to the source terminal of a P-channel transistor Tr120 with a channel length L2 and a channel width W1. The gate terminal of the transistor Tr120 is connected to the second bias voltage terminal VB2, the drain terminal thereof is connected to the current output terminal Iout113, and the source terminal of a P-channel transistor Tr121 with a channel length L1 and a channel width W1 is connected to a power supply VDD, the gate terminal thereof is connected to the first bias voltage terminal VB1 and the drain terminal thereof is connected to the source terminal of a P-channel transistor Tr122 with a channel length L2 and a channel width W1. The gate terminal of the transistor Tr122 is connected to the second bias voltage terminal VB2 and the drain terminal thereof is connected to the current output terminal Iout113, and the source terminal of a P-channel transistor Tr123 with a channel length L1 and a channel width W1 is connected to a power supply VDD, the gate terminal thereof is connected to the first bias voltage terminal VB1 and the drain terminal thereof is connected to the source terminal of a P-channel transistor Tr124 with a channel length L2 and a channel width W1. The gate terminal of the transistor Tr124 is connected to the second bias voltage terminal VB2 and the drain terminal thereof is connected to the current output terminal Iout113. Thus, the current source 113 is able to output a current with a current value corresponding to 4LSB.
FIG. 15 is a layout diagram of the current sources 111 through 113 of FIG. 14. In general, the layout is realized by sharing a diffusion layer by a drain terminal of a transistor with a channel length L1 and a channel width W1 and a source terminal of a transistor with a channel length L2 and a channel width W1.
FIG. 16 is a diagram for showing arrangement of basic circuit blocks in a D/A converter having the current sources of FIG. 14. A circuit block 114 is a transistor matrix part composed of one 1LSB current source 111, one 2LSB current source 112 and sixty-three 4LSB current sources 113. In general, for reducing fabrication variation, the current sources are regularly arranged in the form of a complete matrix by also using dummy current sources so as not to make a gap.
Furthermore, a circuit block 115 is a switch block, where the switches SW1, SW2 and SW3-1 through SW3-63 of FIG. 13 are arranged.
Moreover, a circuit block 116 is a logic circuit including a decoder and the like.
FIG. 17 shows a second exemplified circuit configuration of the conventional current sources.
First, in a current source 119, the source terminal of a P-channel transistor Tr129 with a channel length L3 and a channel width W3 is connected to a power supply VDD, the gate terminal thereof is connected to a first bias voltage terminal VB1 and the drain terminal thereof is connected to the source terminal of a P-channel transistor Tr130 with a channel length L4 and a channel width W3, and the gate terminal of the transistor Tr130 is connected to a second bias voltage terminal VB2 and the drain terminal thereof is connected to a current output terminal Iout119. Thus, the current source 119 is able to output a current with a current value corresponding to 4LSB.
Next, in a current source 118, the source terminal of a P-channel transistor Tr127 with a channel length L3x2 and a channel width W3 is connected to a power supply VDD, the gate terminal thereof is connected to a first bias voltage terminal VB1 and the drain terminal thereof is connected to the source terminal of a P-channel transistor Tr128 with a channel length L4x2 and a channel width W3, and the gate terminal of the transistor Tr128 is connected to a second bias voltage terminal VB2 and the drain terminal thereof is connected to a current output terminal Iout118. Thus, the current source 118 is able to output a current corresponding to a half of the output of the current source 119, namely, a current with a current value corresponding to 2LSB.
Furthermore, in a current source 117, the source terminal of a P-channel transistor Tr125 with a channel length L3x4 and a channel width W3 is connected to a power supply VDD, the gate terminal thereof is connected to a first bias voltage terminal VB1 and the drain terminal thereof is connected to the source terminal of a P-channel transistor Tr126 with a channel length L4x4 and a channel width W3, and the gate terminal of the transistor Tr126 is connected to a second bias voltage terminal VB2 and the drain terminal thereof is connected to a current output terminal Iout117. Thus, the current source 117 is able to output a current corresponding to ¼ of the output of the current source 119, namely, a current with a current value corresponding to 1LSB.
FIG. 18 is a layout diagram of the current sources 117 through 119 of FIG. 17.
FIG. 19 shows a third exemplified circuit configuration of the conventional current sources, which is disclosed in Patent Document 1.
First, in a current source 122, the source terminal of a P-channel transistor Tr137 with a channel length L3, a channel width W3 and multiplier M of 1 is connected to a power supply VDD, the gate terminal thereof is connected to a first bias voltage terminal VB1 and the drain terminal thereof is connected to the source terminal of a P-channel transistor Tr138 with a channel length L4, a channel width W4 and multiplier M of 1, and the gate terminal of the transistor Tr138 is connected to a second bias voltage terminal VB2 and the drain terminal thereof is connected to a current output terminal Iout122. Thus, the current source 122 is able to output a current with a current value corresponding to 4LSB.
Next, in a current source 121, the source terminal of a P-channel transistor Tr134 with a channel length L3, a channel width W3 and multiplier M of 1 is connected to a power supply VDD, the gate terminal thereof is connected to a first bias voltage terminal VB1 and the drain terminal thereof is connected to the source terminal of a P-channel transistor Tr135 with a channel length L4x2, a channel width W4 and multiplier M of 1 and to the source terminal of a P-channel transistor Tr136 with a channel length L4x2, a channel width W4 and multiplier M of 1, and the gate terminals of the transistors Tr135 and Tr136 are connected to a second bias voltage terminal VB2 and the drain terminal of the transistor Tr135 is connected to a current output terminal Iout121, the drain terminal of the transistor Tr136 is connected to the source terminal of a P-channel transistor Tr140 working as a load, and the gate terminal and the drain terminal of the transistor Tr140 are connected to a ground power supply VSS. A 4SLB current passes through the transistor Tr134, and a part of the current corresponding to 2SLB out of the 4SLB current flows to the ground power supply VSS through the transistors Tr136 and Tr140 and the remaining part of the current corresponding to 2LSB is output from the current output terminal Iout121.
Furthermore, in a current source 120, the source terminal of a P-channel transistor Tr131 with a channel length L3, a channel width W3 and multiplier M of 1 is connected to a power supply VDD, the gate terminal thereof is connected to a first bias voltage terminal VB1 and the drain terminal thereof is connected to the source terminal of a P-channel transistor Tr132 with a channel length L4x4, a channel width W4 and multiplier M of 1 and to the source terminal of a P-channel transistor Tr133 with a channel length L4x4, a channel width W4 and multiplier M of 3, and the gate terminals of the transistors Tr132 and Tr133 are connected to a second bias voltage terminal VB2, the drain terminal of the transistor Tr132 is connected to a current output terminal Iout120, the drain terminal of the transistor Tr133 is connected to the source terminal of a P-channel transistor Tr139 working as a load, and the gate terminal and the drain terminal of the transistor Tr139 are connected to a ground power supply VSS. A 4SLB current passes through the transistor Tr131, and a part of the current corresponding to 3SLB out of the 4SLB current flows to the ground power supply VSS through the transistors Tr133 and Tr139 and the remaining part of the current corresponding to 1LSB is output from the current output terminal Iout120.
Patent Document 1: U.S. Pat. No. 6,281,825